1. Field of the Invention
The present invention relates to a semiconductor device to which a bypass capacitor is externally connected.
2. Description of Related Art
Conventionally, as a measure to curb a power source fluctuation of a semiconductor device, there is a case where a bypass capacitor is externally connected between a power source line and a ground line.
In the meantime, as an example of the prior art relevant to the above description, there is JP-A-2009-290841.
However, when a large current flows in the power source lone and the ground line, there is a case where influence of parasitic elements (parasitic inductance component and parasitic resistance component), which reside in the power source line and the ground line, becomes prevailing and it is impossible to sufficiently curb the power source fluctuation of the semiconductor device even if a bypass capacitor is used. Especially in an application whose power source voltage is low, there is a risk that even if a slight power source fluctuation occurs (power source fluctuation that can be neglected in an application whose power source voltage is high), the semiconductor device has trouble in operation.